It was correctly pointed out by that the reset statement should start the if statement not be in the else if. So my question is how to I set up my clock divider module, So that I can access the output register of binary counter and use it to toggle an output when it reaches a certain value.Įrror (10200): Verilog HDL Conditional Statement error at ClockDivider.v(22): cannot match operand(s) in the condition to the corresponding edges in the enclosing event control of the always construct.Ĭlick to expand.Actually the statement always clk or negedge rst) is for a rising edge clock with an active low asynchronous reset and is correct. However this has caused me all sorts of errors. So a tried to connect it to a wire then update new register with the value on that wire. I need to be able to access the output from the counter module "out" however I realised that I couldn't connect a register straight to the output of the previous module.
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |